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CAT24C164 16 kb CMOS Serial EEPROM, Cascadable
Description
The CAT24C164 is a 16 kb CMOS cascadable Serial EEPROM device organized internally as 128 pages of 16 bytes each, for a total of 2048 x 8 bits. The device supports both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol. Data is written by providing a starting address, then loading 1 to 16 contiguous bytes into a Page Write Buffer, and then writing all data to non-volatile memory in one internal write cycle. Data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count. External address pins make it possible to address up to eight CAT24C164 devices on the same bus.
Features
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SOIC-8 W SUFFIX CASE 751BD
TDFN-8 VP2 SUFFIX CASE 511AK
* * * * * * * * * * *
Supports Standard and Fast I2C Protocol 1.8 V to 5.5 V Supply Voltage Range 16-Byte Page Write Buffer Hardware Write Protection for Entire Memory Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA) Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial Temperature Range PDIP, SOIC, TSSOP and TDFN 8-lead Packages This Device is Pb-Free, Halogen Free/BFR Free, and RoHS Compliant
VCC
PDIP-8 L SUFFIX CASE 646AA
TSSOP-8 Y SUFFIX CASE 948AL
PIN CONFIGURATION
A0 A1 A2 VSS 1 VCC WP SCL SDA
PDIP (L), SOIC (W), TSSOP (Y), TDFN (VP2) (Top View) For the location of Pin 1, please consult the corresponding package drawing.
PIN FUNCTION
SCL CAT24C164 SDA Pin Name A0, A1, A2 SDA SCL WP VSS VCC VSS Function Device Address Inputs Serial Data Input/Output Serial Clock Input Write Protect Input Power Supply Ground
A2, A1, A0 WP
Figure 1. Functional Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2009
October, 2009 - Rev. 2
1
Publication Order Number: CAT24C164/D
CAT24C164
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Storage Temperature Voltage on Any Pin with Respect to Ground (Note 1) Ratings -65 to +150 -0.5 to +6.5 Units C V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol NEND (Note 3) TDR Endurance Data Retention Parameter Min 1,000,000 100 Units Program/Erase Cycles Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25C.
Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 1.8 V to 5.5 V, TA = -40C to +85C, unless otherwise specified.)
Symbol ICCR ICCW ISB IL VIL VIH VOL1 VOL2 Read Current Write Current Standby Current I/O Pin Leakage Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage VCC 2.5 V, IOL = 3.0 mA VCC < 2.5 V, IOL = 1.0 mA Parameter Test Conditions Read, fSCL = 400 kHz Write, fSCL = 400 kHz All I/O Pins at GND or VCC Pin at GND or VCC -0.5 VCC x 0.7 Min Max 1 1 1 1 VCC x 0.3 VCC + 0.5 0.4 0.2 Units mA mA mA mA V V V V
Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.8 V to 5.5 V, TA = -40C to +85C, unless otherwise specified.)
Symbol CIN (Note 4) CIN (Note 4) IWP (Note 5) Parameter SDA I/O Pin Capacitance Input Capacitance (other pins) WP Input Current VIN = 0 V VIN = 0 V VIN < VIH, VCC = 5.5 V VIN < VIH, VCC = 3.3 V VIN < VIH, VCC = 1.8 V VIN > VIH Conditions Max 8 6 200 150 100 1 Units pF pF mA
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. 5. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source.
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CAT24C164
Table 5. A.C. CHARACTERISTICS (VCC = 1.8 V to 5.5 V, TA = -40C to +85C.) (Note 6)
Standard Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF (Note 7) tSU:STO tBUF tAA tDH Ti (Note 7) tSU:WP tHD:WP tWR tPU (Notes 7, 8) 6. 7. 8. Clock Frequency START Condition Hold Time Low Period of SCL Clock High Period of SCL Clock START Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Condition Setup Time Bus Free Time Between STOP and START SCL Low to Data Out Valid Data Out Hold Time Noise Pulse Filtered at SCL and SDA Inputs WP Setup Time WP Hold Time Write Cycle Time Power-up to Ready Mode 0 2.5 5 1 100 100 0 2.5 5 1 4 4.7 3.5 100 100 4 4.7 4 4.7 0 250 1000 300 0.6 1.3 0.9 Parameter Min Max 100 0.6 1.3 0.6 0.6 0 100 300 300 Min Fast Max 400 Units kHz ms ms ms ms ms ns ns ns ms ms ms ns ns ms ms ms ms
Test conditions according to "A.C. Test Conditions" table. Tested initially and after a design or process change that affects this parameter. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Levels Input Rise and Fall Times Input Reference Levels Output Reference Levels Output Load 0.2 x VCC to 0.8 x VCC 50 ns 0.3 x VCC, 0.7 x VCC 0.5 x VCC Current Source: IOL = 3 mA (VCC 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
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CAT24C164
Power-On Reset (POR) CAT24C164 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. A CAT24C164 device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR feature protects the device against `brown-out' failure following a temporary loss of power. Pin Description SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master. SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address inputs set the device address when cascading multiple devices. When not driven, these pins are pulled LOW internally. The CAT24C164 can be made compatible with the CAT24C16 by tying A2, A1 and A0 to VSS or by leaving A2, A1 and A0 float. WP: The Write Protect input pin inhibits all write operations, when pulled HIGH. When not driven, this pin is pulled LOW internally. Functional Description The CAT24C164 supports the Inter-Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The CAT24C164 acts as a Slave device. Master and Slave alternate as either transmitter or receiver. I2C Bus Protocol The I2C bus consists of two `wires', SCL and SDA. The two wires are connected to the VCC supply via pull-up resistors. Master and Slave devices connect to the 2-wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to `transmit' a `0' and releases it to `transmit' a `1'. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 2). The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a `wake-up' call to all receivers. Absent a START, a Slave will not respond to commands. The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH.
Device Addressing
The bus Master begins a transmission by sending a START condition. The Master then sends the address of the particular Slave device it is requesting. The most significant bit of the 8-bit slave address is fixed as 1. (see Figure 3). The next three significant bits (A2, A1, A0) are the device address bits and define which device or which part of the device the Master is accessing (The A1 bit must be the compliment of the A1 input pin signal). Up to eight CAT24C164 devices may be individually addressed by the system. The next three bits are used as the three most significant bits of the data word address. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected.
Acknowledge
After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 4). The Slave will also acknowledge the address byte and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. As long as the Master acknowledges the data, the Slave will continue transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by issuing a STOP condition. Bus timing is illustrated in Figure 5.
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CAT24C164
SCL
SDA START CONDITION STOP CONDITION
Figure 2. START/STOP Conditions
1
A2
A1
A0
a10
a9
a8
R/W
CAT24C164
Figure 3. Slave Address Bits
BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER 1 8 9
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT FROM RECEIVER START ACK DELAY ( tAA) ACK SETUP ( tSU:DAT)
Figure 4. Acknowledge Timing
tF tLOW SCL tSU:STA SDA IN tAA SDA OUT tHD:STA
tHIGH tLOW
tR
tHD:DAT
tSU:DAT
tSU:STO
tDH
tBUF
Figure 5. Bus Timing
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CAT24C164
WRITE OPERATIONS
Byte Write
In Byte Write mode, the Master sends the START condition and the Slave address with the R/W bit set to zero to the Slave. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT24C164. After receiving another acknowledge from the Slave, the Master transmits the data byte to be written into the addressed memory location. The CAT24C164 device will acknowledge the data byte and the Master generates the STOP condition, at which time the device begins its internal Write cycle to nonvolatile memory (Figure 6). While this internal cycle is in progress (tWR), the SDA output will be tri-stated and the CAT24C164 will not respond to any request from the Master device (Figure 7).
Page Write
sixteen bytes are received and the STOP condition has been sent by the Master, the internal Write cycle begins. At this point all received data is written to the CAT24C164 in a single write cycle.
Acknowledge Polling
The CAT24C164 writes up to 16 bytes of data in a single write cycle, using the Page Write operation (Figure 8). The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the data byte is transmitted, the Master is allowed to send up to fifteen additional bytes. After each byte has been transmitted the CAT24C164 will respond with an acknowledge and internally increments the four low order address bits. The high order bits that define the page address remain unchanged. If the Master transmits more than sixteen bytes prior to sending the STOP condition, the address counter `wraps around' to the beginning of page and previously transmitted data will be overwritten. Once all
The acknowledge (ACK) polling routine can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, the CAT24C164 initiates the internal write cycle. The ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT24C164 is still busy with the write operation, NoACK will be returned. If the CAT24C164 has completed the internal write operation, an ACK will be returned and the host can then proceed with the next read or write operation.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the CAT24C164. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the first data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the CAT24C164 will not acknowledge the data byte and the Write request will be rejected.
Delivery State
The CAT24C164 is shipped erased, i.e., all bytes are FFh.
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CAT24C164
BUS ACTIVITY: S T A MASTER R T S SLAVE A C K A C K A C K SLAVE ADDRESS ADDRESS BYTE a7 - a0 DATA BYTE d7 - d0 S T O P P
Figure 6. Byte Write Sequence
SCL
SDA
8th Bit Byte n
ACK tWR STOP CONDITION START CONDITION ADDRESS
Figure 7. Write Cycle Timing
BUS ACTIVITY: MASTER
S T A R T S
SLAVE ADDRESS
ADDRESS BYTE
DATA BYTE n
DATA BYTE n+1
DATA BYTE n+P
S T O P P A C K
SLAVE n=1 P 15
A C K
A C K
A C K
A C K
Figure 8. Page Write Sequence
ADDRESS BYTE 1 SCL 8 9 1
DATA BYTE 8
SDA
a7
a0 tSU:WP
d7
d0
WP tHD:WP
Figure 9. WP Timing
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CAT24C164
READ OPERATIONS
Immediate Read
Upon receiving a Slave address with the R/W bit set to `1', the CAT24C164 will interpret this as a request for data residing at the current byte address in memory. The CAT24C164 will acknowledge the Slave address, will immediately shift out the data residing at the current address, and will then wait for the Master to respond. If the Master does not acknowledge the data (NoACK) and then follows up with a STOP condition (Figure 10), the CAT24C164 returns to Standby mode.
Selective Read
address of the location it wishes to read. After the CAT24C164 acknowledges the byte address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The CAT24C164 then responds with its acknowledge and sends the requested data byte. The Master device does not acknowledge the data (NoACK) but will generate a STOP condition (Figure 11).
Sequential Read
Selective Read operations allow the Master device to select at random any memory location for a read operation. The Master device first performs a `dummy' write operation by sending the START condition, slave address and byte
BUS ACTIVITY: MASTER S T A R T S SLAVE A C K
If during a Read session, the Master acknowledges the 1st data byte, then the CAT24C164 will continue transmitting data residing at subsequent locations until the Master responds with a NoACK, followed by a STOP (Figure 12). In contrast to Page Write, during Sequential Read the address count will automatically increment to and then wrap-around at end of memory (rather than end of page).
N O
SLAVE ADDRESS
S AT CO KP P
DATA BYTE
SCL
8
9
SDA
8th Bit DATA OUT NO ACK STOP
Figure 10. Immediate Read Sequence and Timing
BUS ACTIVITY: MASTER S T A R T S SLAVE A C K A C K S T A R T S A C K DATA BYTE N O A C K
SLAVE ADDRESS
ADDRESS BYTE
SLAVE ADDRESS
S T O P P
Figure 11. Selective Read Sequence
BUS ACTIVITY: MASTER SLAVE ADDRESS A C K A C K A C K N O A C K
S T O P P
SLAVE
A C K
DATA BYTE n
DATA BYTE n+1
DATA BYTE n+2
DATA BYTE n+x
Figure 12. Sequential Read Sequence
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CAT24C164
PACKAGE DIMENSIONS
PDIP-8, 300 mils CASE 646AA-01 ISSUE A
SYMBOL A A1 A2 b E1 b2 c D E E1 e eB PIN # 1 IDENTIFICATION D L 7.87 2.92 3.30 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 BSC 10.92 3.80 4.95 0.56 1.78 0.36 10.16 8.25 7.11 MIN NOM MAX 5.33
TOP VIEW E
A
A2
A1 b2 L c
e SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001.
b
eB
END VIEW
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CAT24C164
PACKAGE DIMENSIONS
SOIC 8, 150 mils CASE 751BD-01 ISSUE O
SYMBOL A A1 b c E1 E D E E1 e h L PIN # 1 IDENTIFICATION TOP VIEW 0.25 0.40 MIN 1.35 0.10 0.33 0.19 4.80 5.80 3.80 1.27 BSC 0.50 1.27 NOM MAX 1.75 0.25 0.51 0.25 5.00 6.20 4.00
0
8
D
h
A1
A
c e SIDE VIEW b L END VIEW
Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012.
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CAT24C164
PACKAGE DIMENSIONS
TSSOP8, 4.4x3 CASE 948AL-01 ISSUE O
b
SYMBOL
A A1 A2 b E1 E c D E E1 e L L1
MIN
0.05 0.80 0.19 0.09 2.90 6.30 4.30
NOM
MAX
1.20 0.15
0.90
1.05 0.30 0.20
3.00 6.40 4.40 0.65 BSC 1.00 REF
3.10 6.50 4.50
0.50
0.60
0.75
e
0
8
TOP VIEW D
A2
A
q1
c
A1 SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153.
L1 END VIEW
L
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CAT24C164
PACKAGE DIMENSIONS
TDFN8, 2x3 CASE 511AK-01 ISSUE A
D A e b
E
E2 PIN#1 IDENTIFICATION
A1 PIN#1 INDEX AREA D2 L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL A A1 A2 A3 b D D2 E E2 e L
MIN 0.70 0.00 0.45 0.20 1.90 1.30 2.90 1.20 0.20
NOM 0.75 0.02 0.55 0.20 REF 0.25 2.00 1.40 3.00 1.30 0.50 TYP 0.30
MAX 0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.40 0.40 FRONT VIEW A2 A3
Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-229.
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CAT24C164
Package Marking
8-Lead PDIP 8-Lead SOIC
24C164LI FYYWW G
I YY WW G F = Temperature Range = Production Year = Production Week = Product Revision = Lead Finish = 4 = NiPdAu
24C164WI FYYWWG
I YY WW G F
= Temperature Range = Production Year = Production Week = Product Revision = Lead Finish = 4 = NiPdAu
8-Lead TSSOP
8-Pad TDFN
YMGF 24164I
Y M G I F = Production Year = Production Month = Die Revision = Temperature Range = Lead Finish = 4 = NiPdAu
XXN NNN YM
XX N Y M = Device Code = FR = NiPdAu = Traceable Code = Production Year = Production Month
9. The circle on the package marking indicates the location of Pin 1. 10. For TDFN package, the Product Revision marking is included in the Device Code (XX).
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CAT24C164
Example of Ordering Information
Prefix CAT Device # 24C164 Suffix Y I -G T3
Company ID Product Number 24C164
Temperature Range I = Industrial (-40C to +85C) E = Extended (-40C to +125C)
Lead Finish G: NiPdAu
Tape & Reel (Note 16) T: Tape & Reel 3: 3,000 / Reel
Package L: PDIP W: SOIC, JEDEC Y: TSSOP VP2: TDFN
ORDERING INFORMATION
Orderable Part Numbers
CAT24C164LI-G CAT24C164WI-GT3 CAT24C164YI-GT3 CAT24C164VP2IGT3 (Note 15) CAT24C164LE-G CAT24C164WE-GT3 CAT24C164YE-GT3 CAT24C164VP2EGT3 (Note 15)
11. All packages are RoHS-compliant (Lead-free, Halogen-free). 12. The standard lead finish is NiPdAu. 13. The device used in the above example is a CAT24C164YI-GT3 (TSSOP, Industrial Temperature, NiPdAu, Tape & Reel, 3,000/Reel). 14. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 15. Part number is not exactly the same as the "Example of Ordering Information" shown above. For the part numbers indicated there are NO hyphens in the orderable part numbers. 16. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CAT24C164/D

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